Galois field hardware architectures for network coding
Galois field hardware architectures for network coding
复制标题
用于网络编码的伽罗瓦现场硬件架构
DOI：
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发表时间：
2010
期刊：
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通讯作者：
P. Ramanathan
中科院分区：
文献类型：
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作者：
Aishwarya Nagarajan;M. Schulte;P. Ramanathan
本文提出并分析了新的高速网络编码的硬件设计。我们的设计提供了有效的方法来执行伽罗瓦域（GF）的点积和矩阵求逆，这是网络编码中的重要操作。编码器设计，执行GF点积，并根据组合的消息的数量，伽罗瓦字段的大小，和输入消息的大小进行了实施和分析，以评估设计权衡。我们调查单周期，多线程，和流水线设计，并没有反馈机制编码多组消息。解码器被实现为多周期设计，并执行GF矩阵求逆，然后执行多个GF点积。我们的设计与65纳米标准单元库合成，并在面积，关键路径延迟和吞吐量方面进行比较。结合四个消息的设计实现了超过30 Gbps的吞吐量。我们的设计可以通过使用额外的硬件来扩展，以实现更高的吞吐量。
This paper presents and analyzes novel hardware designs for high-speed network coding. Our designs provide efficient methods to perform Galois field (GF) dot products and matrix inversions, which are important operations in network coding. Encoder designs that perform GF dot products and vary with respect to the number of messages combined, Galois field size, and input message size are implemented and analyzed to evaluate design tradeoffs. We investigate single cycle, multicycle, and pipelined designs with and without feedback mechanisms for encoding multiple sets of messages. The decoder is implemented as a multi-cycle design and performs GF matrix inversion followed by multiple GF dot products. Our designs are synthesized with a 65nm standard cell library and compared in terms of area, critical path delay, and throughput. Designs combining four messages achieve throughputs of more than 30 Gbps. Our designs can scale to achieve much higher throughput through the use of additional hardware.