A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier
A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier
复制标题
具有低功耗像素内 NMOS 无源放大器的 20 Mfps 高帧深度 CMOS 突发模式成像器
DOI：
10.1117/12.2271135
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
J. Borremans
中科院分区：
文献类型：
--
作者：
L. Wu;D. San Segundo Bello;P. Coppejans;J. Craninckx;P. Wambacq;J. Borremans
本文介绍了一种20MFPS、32×84像素的高帧深、带无源像素内放大器的CMOS型突发模式成像器。与CCD相比，CMOS型突发模式成像器因其低功耗和与ADC等电路集成而具有吸引力。由于存储电容的尺寸及其噪声限制，CMOS猝发模式成像器的帧深度通常比CCD实现的低。为了在更长的时间跨度上捕获快速转变，采用了像素内CDS技术，将每帧所需的存储单元减少了一半。此外，与像素内CDS集成后，仅支持NMOS的像素内无源放大器降低了存储体的KTC噪声要求，从而允许使用更小的电容器。具体地说，已经在30μm间距像素内实现了密集的108单元MOS存储体(10fF/单元)，该存储体占据了25×30μm2的面积。通过应用像素内CDS和放大，每像素区的帧深度提高了约4倍。在放大器增益为3.3的情况下，在20 Mfps的工作状态下，FD输入参考的均方根噪声为1 mV。虽然放大是在没有消耗直流电流的情况下完成的，包括像素源跟随器偏置，但在全速下，整个像素在3.3V电源电压下消耗10μA。该芯片采用IMEC的130 nm CMOSCIS工艺制造。
This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier’s gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec’s 130nm CMOS CIS technology.