Impact of TSV proximity on 45nm CMOS devices in wafer level-猫眼课题宝

DOI：

10.1109/iitc.2011.5940326

发表时间：

2011-05

期刊：

2011 IEEE International Interconnect Technology Conference

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通讯作者：

中科院分区：

其他

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作者：

Sungdong Cho;Sinwoo Kang;Kangwook Park;Jaechul Kim;Kiyoung Yun;Kisoon Bae;W. S. Lee;S. Ji;

在晶圆级上评估了硅通孔（TSV）邻近对各种45nm CMOS器件的影响。直径为6 μ m的Cu填充TSV× 55 μ m（高）的半导体芯片采用“中间通孔”工艺形成。在完成BEOL模块工艺之后，使用未减薄的晶片进行电测量。通常，由于TSV而引起的器件性能变化在小于2um的距离内观察到，但最大变化小于2%。还确定了TSV影响的理论和真实的数据之间的差异。

Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using ‘via middle’ process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Mostly the device performance change due to TSV is observed in less than 2um distance but the change is less than 2% in maximum. Also discrepancy between theory and real data on TSV impact was identified.

Impact of TSV proximity on 45nm CMOS devices in wafer level

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