Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology
Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology
复制标题
硅纳米线 CMOS 技术特性可变性的实验研究和设计优化指南
DOI：
--
复制
发表时间：
2009
期刊：
影响因子：
--
通讯作者：
Yangyuan Wang
中科院分区：
文献类型：
--
作者：
J. Zhuge;Runsheng Wang;Ru Huang;Jibin Zou;Xin Huang;D. Kim;Donggun Park;Xing Zhang;Yangyuan Wang
本文对栅通绕硅纳米线MOSFET(SNWTs)的特性变异性进行了实验研究。考虑了强受限几何诱导的量子效应、准弹道效应以及一维沟道和三维S/D宽区域界面的寄生量子电阻，首次提取了单边带中的变化源。测量结果表明，在本征沟道中随机掺杂起伏(RDF)被抑制的情况下，SNWT的半径(R)和金属栅功函数(WF)的变化同时控制了阈值电压和导通电流的起伏，而线边缘粗糙度(LER)的影响很小。估计了SNWT变化源对SRAM性能的影响，并与平面器件进行了比较。除了工艺变化外，还研究了随机电报信号(RTS)噪声在SNWT中引起的变化，以评估SRAM单元的工作窗口。根据对SRAM变化的分析结果，给出了设计优化准则。
In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured results show that with suppressed random dopant fluctuations (RDF) in the intrinsic channel, variations in radius (R) and metal-gate work function (WF) of SNWTs dominate both the threshold voltage and on-current fluctuations, and line-edge-roughness (LER) shows minor impact. The influence of the SNWT variation sources on SRAM performance is estimated and compared with planar devices. In addition to process variation, variation induced by random telegraph signal (RTS) noise in SNWTs is also investigated for the evaluation of SRAM cell operating window. Design optimization guidelines are given based on the SRAM variation analyzed results.