Exploration of TMR fault masking with persistent threads on Tegra GPU SoCs
Exploration of TMR fault masking with persistent threads on Tegra GPU SoCs
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在 Tegra GPU SoC 上使用持久线程探索 TMR 故障屏蔽
DOI：
10.1109/aero.2017.7943882
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
A. George
中科院分区：
文献类型：
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作者：
Andrew Milluzzi;A. George
低功耗、高性能的片上系统（SoC）器件，如NVIDIA Tegra K1和Tegra X1，在航空航天应用中具有许多潜在用途。Tegra SoC融合了ARM CPU和大型GPU，非常适合图像和信号处理。然而，GPU上的故障屏蔽和容错对于恶劣环境相对来说是未开发的。Tegra SoC拥有数百个GPU内核、复杂的缓存结构和自定义任务调度器，因此容易受到各种单事件翻转（SEU）的影响。三模冗余（TMR）为各种设备的故障屏蔽提供了坚实的基础。GPU对典型的TMR实现提出了独特的挑战。NVIDIA的调度程序根据可用资源分配任务，但调度过程没有公开记录。因此，可以在每个TMR模块中为故障核心分配相同的代码块。在这种情况下，故障可能无法检测到，从而导致产生错误的数据。同样，调度程序或缓存中的混乱可能对数据完整性产生不利影响。为了屏蔽和减轻GPU中的干扰，我们提出并研究了一种新的方法，该方法具有持久线程和CUDA流与TMR。持久线程是GPU编程的一种新方法，其中内核的线程无限期地运行。CUDA流使多个内核能够在单个GPU上并发运行。结合这两种编程范式，我们消除了调度器故障的漏洞，并确保每个迭代在不同的核心上同时执行，每个实例都有自己的数据副本。我们通过一个实验来评估我们的方法，该实验使用Sobel滤波器应用于NVIDIA Tegra X1上的640×480图像。为了注入错误来验证我们的方法，一个单独的任务破坏了一个内存位置。使用这个简单的注入器，我们能够模拟GPU核心或内存位置的翻转。通过该实验，我们的结果证实了使用持久线程和CUDA流以及TMR屏蔽了Tegra X1上的模拟SEU。此外，我们提供的性能结果，以量化的开销与这种新的方法。
Low-power, high-performance, System-on-Chip (SoC) devices, such as the NVIDIA Tegra K1 and Tegra X1, have many potential uses in aerospace applications. Fusing ARM CPUs and a large GPU, Tegra SoCs are well suited for image and signal processing. However, fault masking and tolerance on GPUs is relatively unexplored for harsh environments. With hundreds of GPU cores, a complex caching structure, and a custom task scheduler, Tegra SoCs are vulnerable to a wide range of single-event upsets (SEUs). Triple-modular redundancy (TMR) provides a strong basis for fault masking on a wide range of devices. GPUs pose a unique challenge to a typical TMR implementation. NVIDIA's scheduler assigns tasks based on available resources, but the scheduling process is not publicly documented. As a result, a malfunctioning core could be assigned the same block of code in each TMR module. In this case, a fault could go undetected, impacting the resulting data with an error. Likewise, an upset in the scheduler or cache could have an adverse impact on data integrity. In order to mask and mitigate upsets in GPUs, we propose and investigate a new method that features persistent threading and CUDA Streams with TMR. A persistent thread is a new approach to GPU programming where a kernel's threads run indefinitely. CUDA Streams enable multiple kernels to run concurrently on a single GPU. Combining these two programming paradigms, we remove the vulnerability of scheduler faults, and ensure that each iteration is executed concurrently on different cores, with each instance having its own copy of the data. We evaluate our method with an experiment that uses a Sobel filter applied to a 640×480 image on an NVIDIA Tegra X1. In order to inject faults to verify our method, a separate task corrupts a memory location. Using this simple injector, we are able to simulate an upset in a GPU core or memory location. From this experiment, our results confirm that using persistent threading and CUDA Streams with TMR masks the simulated SEUs on the Tegra X1. Furthermore, we provide performance results to quantify the overhead with this new method.