Wafer-level bonding/stacking technology for 3D integration
Wafer-level bonding/stacking technology for 3D integration
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DOI：
10.1016/j.microrel.2009.09.015
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发表时间：
2010-04-01
影响因子：
1.6
通讯作者：
Chen, Kuan-Neng
中科院分区：
文献类型：
--
作者：
Ko, Cheng-Ta;Chen, Kuan-Neng
据报道，在许多设备和应用中，使用3D集成时，传输速度更快、功耗更低、性能更好和外形尺寸更小都是优势。用于执行3D互连的一个核心技术是堆叠接合。本文对圆片级键合技术进行了详细的回顾和描述，包括键合材料和键合条件。同时，还对世界范围内开发的三维集成技术和平台进行了梳理和讨论。(C)2009爱思唯尔有限公司版权所有。
Enhanced transmission speeds, lower power consumption, better performance, and smaller form factors are reported as advantages in many devices and applications when using 3D integration. One core technique for performing 3D interconnection is stacked bonding. In this paper, wafer-level bonding technologies are reviewed and described in detail, including bonding materials and bonding conditions. The corresponding 3D integration technologies and platforms developed world-wide are also organized and addressed. (C) 2009 Elsevier Ltd. All rights reserved.