Analysis and reduction of SRAM PUF Bit Error Rate

Analysis and reduction of SRAM PUF Bit Error Rate
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SRAM PUF误码率分析及降低

DOI：
10.1109/vlsi-dat.2017.7939688
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发表时间：
2017
期刊：
2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
影响因子：
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通讯作者：
Shiyu Liu
Shiyu Liu
中科院分区：
--
文献类型：
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作者：
H. Shinohara;B. Zheng;Yanhao Piao;Bo Liu;Shiyu Liu

文献摘要

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降低误码率是物理不可克隆函数在安全应用中的一个关键问题。本文从失配因子和噪声两个主要因素对误码率进行了分析。通过比较5个不同晶体管尺寸的SRAM PUF，提取了决定失配的负载pMOS和驱动nMOS的权重因子。研究表明，通过改变pMOS/nMOS晶体管尺寸比可以降低误码率。
Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.