An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces
An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces
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DOI:
10.1109/tbcas.2019.2963302
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发表时间:
2020-04-01
影响因子:
5.1
通讯作者:
Heydari, Payam
中科院分区:
文献类型:
--
作者:
Malekzadeh-Arasteh, Omid;Pu, Haoran;Heydari, Payam
This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high-. band (80-160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72x power reduction in the analog blocks and up to 50xpotential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05 mu W (0.205 mu Wf or feature extraction only) power and occupies 0.245mm2 die area per channel. The chipmeasurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). Invivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.