Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
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DOI：
10.1109/vlsi-dat52063.2021.9427353
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发表时间：
2021-04
期刊：
影响因子：
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通讯作者：
M. Kabir;Weishiun Hung;Tsung-Yi Ho;Yarui Peng
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作者：
M. Kabir;Weishiun Hung;Tsung-Yi Ho;Yarui Peng
近年来，随着越来越多的异构小芯片集成到先进的系统级封装中，2.5D封装设计越来越受欢迎。RDL连线变得越来越长，越来越密集，对系统性能、可靠性和完整性的影响越来越大。目前，还没有一个标准的CAD流程可以设计、分析和优化一个完整的异构2.5D系统。传统的逐模设计方法在提取和优化过程中独立处理每个组件，如果不对标准CAD工具进行根本更改，则无法应用于异构系统。不仅忽略了所有RDL电容和电感影响的芯片封装提取不准确，而且传统的CAD工具也无法进行跨界设计优化。（p/）(p)我们提出了一个完整的芯片-封装协同优化流程，适用于均匀和非均匀的2.5D设计。它包括2.5D感知划分、芯片封装协同规划、整体和上下文提取、封装电感考虑和迭代优化，以及整个2.5D系统的设计分析和验证。在我们之前针对异构系统的工作[1]中，我们实现了在-2.10%到24.0%之间的提取误差。本文提出的上下文设计流程在接地和耦合电容上的提取误差小于1%。该提取结果可用于以99.8%的准确率进行时序分析，并以99.4%的准确率生成时序上下文进行迭代优化。
In recent days, 2.5D package designs have gained popularity with an increasing number of heterogeneous chiplets integrated into advanced system-in-packages. RDL wires become longer and denser, presenting a growing impact on system performance, reliability, and integrity. At present, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die-by-die design approach processes each component independently during extraction and optimization and cannot be applied to heterogeneous systems without fundamental changes in standard CAD tools. Not only the chiplet-package extraction is inaccurate between the die-package interface ignoring all RDL capacitive and inductive impacts, but traditional CAD tools are also unable to perform cross-boundary design optimization.(p/)(p)We present a complete chiplet-package co-optimization flow for both homogeneous and heterogeneous 2.5D designs. It encompasses 2.5D-aware partitioning, chiplet-package co-planning, holistic and in-context extraction, package inductance consideration, and iterative optimization, along with design analysis and verification of the entire 2.5D system. In our previous work [1] targeting heterogeneous systems, we achieved an extraction error ranging between -2.10% and 24.0%. The in-context design flow proposed in this work achieves less than 1% extraction error on ground and coupling capacitance. This extraction result can be used to perform timing analysis with 99.8% accuracy and to generate timing context with 99.4% accuracy for iterative optimization.