Design and implementation of enhanced crossbar CIOQ switch architecture
Design and implementation of enhanced crossbar CIOQ switch architecture
复制标题
增强型Crossbar CIOQ交换机架构的设计与实现
DOI：
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
R. Venkatesan
中科院分区：
文献类型：
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作者：
A. Awan;R. Venkatesan
目前，组合输入输出排队（CIOQ）交换机正在考虑高性能的交换机架构。这是因为它们能够实现高吞吐量，并以4或5的小加速因子模拟输出排队交换机性能。本文介绍了一种基于16/spl times/16信元的CIOQ交换机的设计和VLSI实现，该交换机具有增强的交叉开关，在以线速操作交换结构和以一半线速操作存储器的同时，提供4的加速比。我们描述了这种架构在VLSI中使用0.18微米CMOS标准单元技术的实施。我们报告的设计复杂性，并讨论实施结果。该架构可以处理622 Mbps的线路速率。分布式小区调度和小区调度和去调度允许该架构被缩放到大量的输入和输出。
Currently, combined input output queued (CIOQ) switches are being considered for high performance switch architectures. This is due to their ability to achieve high throughput and emulate output queued switch performance with a small speedup factor of 4 or 5. The paper presents the design and VLSI implementation of a 16/spl times/16 cell based CIOQ switch with enhanced crossbars to provide a speedup of 4 while operating the switch fabric at the line rate and memories at half the line rate. We describe the implementation of this architecture in VLSI using 0.18 micron CMOS standard-cell technology. We report on the design complexity and discuss implementation results. This architecture can handle a line rate of 622 Mbps. The distributed cell scheduling and cell queueing and dequeueing allows this architecture to be scaled to a large number of inputs and outputs.