3 D-stacking architecture for low-noise high-speed image sensors
3 D-stacking architecture for low-noise high-speed image sensors
复制标题
用于低噪声高速图像传感器的 3D 堆叠架构
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
S. Kawahito
中科院分区：
文献类型：
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作者：
S. Kawahito
本文讨论了基于三维叠层技术的低噪声高速图像传感器结构。在基于12位3级循环流水线ADC的33Mpixel 240fps 3D堆栈CMOS图像传感器的实现中，证明了低噪声高速图像传感器的3D堆栈技术的有效性。为了实现极低噪声和宽动态范围成像，基于多路复用器的高并行ADC将成为三维堆叠CMOS图像传感器的重要技术。
In this paper, architectures for low-noise high-speed image sensors based on 3D stacking technology are discussed. Effectiveness of the 3D-stacking technology for low-noise high-speed image sensors is demonstrated in an implementation of a 33Mpixel 240fps 3D-stacked CMOS image sensor based on 12b 3-stage cyclic-based pipelined ADCs. For extremely low noise and wide dynamic range imaging, highly-parallel multiplesampling based ADC will be an important technique for 3-D stacked CMOS image sensors.