III-V/Ge channel MOS device technologies in nano CMOS era
III-V/Ge channel MOS device technologies in nano CMOS era
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DOI：
10.7567/jjap.54.06fa01
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发表时间：
2015-06-01
影响因子：
1.5
通讯作者：
Takenaka, Mitsuru
中科院分区：
文献类型：
--
作者：
Takagi, Shinichi;Zhang, Rui;Takenaka, Mitsuru
在Si衬底上利用高迁移率III-V/Ge通道的CMOS由于其增强的载流子传输特性，有望成为未来高性能和低功耗高级lsi的有前途的器件之一。然而，在Si平台上实现基于III-V/Ge的CMOS存在许多关键问题和困难挑战，如：(1)在Si衬底上形成高晶体质量的Ge/III-V薄膜，(2)栅极堆叠技术以实现卓越的MOS/MIS接口质量，(3)形成低电阻率和低漏电流的源/漏极（S/D），(4)实现超短通道器件的工艺集成，以及(5)包括Si CMOS在内的CMOS整体集成。在本文中，我们回顾了III-V/Ge MOS器件和工艺技术的最新进展，作为解决上述关键问题的可行方法。这些技术包括MOS栅极堆叠形成、高质量沟道形成、低电阻S/D形成和CMOS集成。对于锗器件技术，我们主要关注栅极堆叠技术和在硅上形成锗通道。此外，对于III-V MOS器件技术，我们主要解决栅极堆栈技术，Si上的III-V沟道形成，金属S/D技术，以及将这些技术实现为Si衬底上的短沟道III-V- oi mosfet。在现有研究成果的基础上，讨论了利用III-V/Ge通道实现各种CMOS结构的可能性。(C) 2015日本应用物理学会
CMOS utilizing high-mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III-V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III-V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III-V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III-V MOS device technologies, we mainly address the gate stack technology, III-V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III-V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III-V/Ge channels. (C) 2015 The Japan Society of Applied Physics