A 700uA, 405MHz fractional-N All digital frequency-locked loop for MICS band applications
A 700uA, 405MHz fractional-N All digital frequency-locked loop for MICS band applications
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适用于 MICS 频段应用的 700uA、405MHz 小数 N 分频全数字锁频环
DOI：
10.1109/rfic.2010.5477249
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
B. Bakkaloglu
中科院分区：
文献类型：
--
作者：
S. Shashidharan;W. Khalil;S. Chakraborty;S. Kiaei;T. Copani;B. Bakkaloglu
提出了一种基于全数字锁频环（ADFLL）的内置FSK调制器的频率合成器，用于医疗植入物通信系统（MICS）频段的应用。ADFLL在反馈路径中使用高分辨率的单比特数字ΣΔ鉴频器，在参考路径中使用ΣΔ相位累加器，实现分数阶分辨率。ADFLL使用一个基于数字iir的环路滤波器，然后是一个数字密集型ΣΔ电流转向DAC和一个一阶保持滤波器。ADFLL实现9.5Hz频率分辨率，跨越ISM 400MHz-410MHz频段。在300kHz偏置时，最坏情况下的近整数杂散为- 55dBc，相位噪声为- 83dBc/Hz。ADFLL采用0.18um CMOS工艺制造，占地0.14mm2芯片面积，静态电流消耗为700uA。
An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of −55dBc and a phase noise of −83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.