Wrapper design for multifrequency IP cores
Wrapper design for multifrequency IP cores
复制标题
多频 IP 核的包装设计
DOI：
10.1109/tvlsi.2005.848811
复制
发表时间：
2005
影响因子：
2.8
通讯作者：
N. Nicolici
中科院分区：
文献类型：
--
作者：
Qiang Xu;N. Nicolici
本文讨论了多个时钟域的知识产权核提出的可测性问题。所提出的解决方案是基于一种新的核心包装器架构和一种新的包装器设计算法。它示出了如何多频高速测试响应捕获可以通过捕获窗口的设计来实现，而无需对嵌入式内核内的逻辑进行任何结构修改。核心包装器架构中的新功能引入了有限的硬件开销，也可以在移位模式下将外部测试仪通道与核心的内部扫描链同步。因此，可以探索包装器实现空间，以便有效地利用可用的测试器带宽，同时满足对最大内部移位频率的约束，该最大内部移位频率保证给定额定功率内的低测试时间。使用实验数据，所提出的解决方案的好处是通过分析测试通道的数量，测试时间，面积开销和功耗之间的权衡证明。
This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via the design of capture windows without any structural modifications to the logic within the embedded core. The new features in the core wrapper architecture, which introduce limited hardware overhead, can also synchronize the external tester channels with the core's internal scan chains in the shift mode. Thus, the wrapper implementation space can be explored in order to efficiently utilize the available tester bandwidth while meeting the constraints on the maximum internal shift frequency that guarantees low testing time within the given power ratings. Using experimental data, the benefits of the proposed solution are demonstrated by analyzing the tradeoffs between the number of tester channels, testing time, area overhead, and power dissipation.