Parallel Unary Computing Based on Function Derivatives
Parallel Unary Computing Based on Function Derivatives
复制标题
基于函数导数的并行一元计算
DOI：
10.1145/3418464
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Yuyang Li
中科院分区：
文献类型：
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作者：
S. Mohajer;Zhiheng Wang;K. Bazargan;Yuyang Li
二进制数表示法由于其紧凑的存储要求，几十年来一直主导着数字逻辑。另一种表示是一元数制：我们使用N位，其中前M位为1，其余为0来表示值M/N。单位制表示是一元数字系统的一种变体，它在N位中有一个1，其中1的位置表示它的值。我们提出了一种新颖的方法，首先使用温度计（单热）编码器将二进制数转换为一元，然后使用“缩放网络”，然后使用我们称为“交流发电机逻辑”的投票门，然后使用解码器将数字转换回二进制格式。对于单调递增的函数，我们只需要缩放网络，它本质上只使用典型FPGA架构上的路由资源和触发器。我们的方法明显优于传统的二进制实现：在温度计编码方案中，对于8位、10位和12位分辨率，我们的area×delay成本平均仅为二进制方法的0.4%、4%和39%，在单热编码方案中分别为0.5%、15%和147%。在功率效率方面，我们的单热方法比传统二进制方法好69到114倍。
The binary number representation has dominated digital logic for decades due to its compact storage requirements. An alternative representation is the unary number system: We use N bits, from which the first M are 1 and the rest are 0 to represent the value M/N. One-hot representation is a variation of the unary number system where it has one 1 in the N bits, where the 1’s position represents its value. We present a novel method that first converts binary numbers to unary using thermometer (one-hot) encoders and then uses a “scaling network” followed by voting gates that we call “alternator logic,” followed by a decoder to convert the numbers back to the binary format. For monotonically increasing functions, the scaling network is all we need, which essentially uses only the routing resources and flip-flops on a typical FPGA architecture. Our method is clearly superior to the conventional binary implementation: Our area×delay cost is on average only 0.4%, 4%, and 39% of the binary method for 8-, 10-, and 12-bit resolutions, respectively, in thermometer encoding scheme, and 0.5%, 15%, and 147% in the one-hot encoding scheme. In terms of power efficiency, our one-hot method is between about 69× and 114× better compared to conventional binary.