ASIC/SoC Functional Design Verification
ASIC/SoC Functional Design Verification
复制标题
ASIC/SoC 功能设计验证
DOI：
10.1007/978-3-319-59418-7
复制
发表时间：
2018
影响因子：
1.7
通讯作者：
Ashok B. Mehta
中科院分区：
文献类型：
--
作者：
Ashok B. Mehta
作为一名 CPU 和 SoC 设计和验证工程师超过 20 年，我逐渐意识到设计验证领域的广度和深度都非常详尽。仅了解 SystemVerilog 和 UVM 可能还不够。当然，您需要了解UVM（通用验证方法），还需要了解SVA（SystemVerilog断言）、SFC（SystemVerilog功能覆盖）、CRV（约束随机验证）、CDC（时钟域交叉）验证、互连NoC（片上网络）验证、AMS（模拟/混合信号）验证、低功耗验证（UPF）、硬件加速和仿真、硬件/软件 协同验证，以及静态形式（又名静态功能，又名形式属性检查）验证技术和方法。我注意到没有一本书可以很好地概述（高水平但有足够的细节）现有的技术和方法。工程师依靠白皮书、博客和 EDA 供应商文献来了解其中许多主题。这就是这本书的动力。我在本书中涵盖了所有上述主题。
Having been a design and verification engineer of CPUs and SoCs for over 20 years, I’ve come to realize that the design verification field is very exhaustive in its breadth and depth. Knowing only SystemVerilog and UVM may not suffice. Sure, you need to know UVM (Universal Verification Methodology) but also SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CRV (constrained random verification), CDC (clock domain crossing) verification, interconnect NoC (Network on Chip) verification, AMS (analog/mixed signal) verification, low-power verification (UPF), hardware acceleration and emulation, hardware/software co-verification, and static formal (aka static functional aka formal property check) verification technologies and methodologies.I noticed that there isn’ta book that gives a good overview (high level but with sufficient detail) of the technologies and methodologies at hand. Engineers rely on white papers, blogs, and EDA vendor literature to get some understanding of many of these topics. That was the impetus for this book. I have covered all the aforementioned topics in this book.