ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
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ACCORD：通过协调路安装和路预测来实现千兆级 DRAM 缓存的关联性
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Moinuddin K. Qureshi
中科院分区：
文献类型：
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作者：
Vinson Young;Chiachen Chou;A. Jaleel;Moinuddin K. Qureshi
堆叠式DRAM技术已经实现了高带宽千兆级DRAM高速缓存。由于DRAM高速缓存需要几十兆字节的标签存储，因此商业DRAM高速缓存设计通常将标签和数据共同定位在DRAM阵列内。DRAM缓存被组织为直接映射结构，以便标签和数据可以在单个访问中流出。虽然直接映射的DRAM高速缓存提供低命中等待时间，但它们由于冲突未命中而遭受低命中率。理想情况下，我们希望集关联DRAM缓存的命中率，而不会产生增加关联性的额外延迟和带宽成本。为了解决这个问题，路预测可以应用于组关联DRAM高速缓存以实现直接映射DRAM高速缓存的延迟和带宽。不幸的是，传统的路径预测策略通常需要每集存储，导致千兆级DRAM高速缓存的多兆字节存储开销。如果我们可以获得准确的路径预测，而不会产生显着的存储开销，我们可以有效地启用DRAM缓存的集合关联性。本文提出了通过协调的方式安装和方式预测（雅阁），一种设计，引导一个传入的线路到一个“首选方式”的基础上的线路地址，并使用首选的方式作为默认的方式预测的关联性。我们提出了两种有效的双向缓存的指导政策。首先，概率路径转向（PWS），它以高概率将线路转向首选的方式，同时在冲突的情况下仍然允许线路以替代方式安装。第二，联动转向（GWS），它将空间连续区域的线路转向该区域的早期线路安装的方式。在2路缓存上，雅阁（PWS+GWS）获得90%的路预测准确度，并保持与基线2路缓存相似的命中率，同时产生320字节的存储开销。我们扩展雅阁，以支持高度关联的高速缓存，使用一个歪斜的方式转向（SWS）的设计，引导一行至多两个方式在高度关联的高速缓存。该设计保留了2路雅阁的低延迟，同时获得了高度关联设计的大部分命中率优势。我们对由非易失性存储器支持的4GB DRAM缓存的研究表明，雅阁在各种工作负载上提供了平均11%的加速比（高达54%）。
Stacked-DRAM technology has enabled high bandwidth gigascale DRAM caches. Since DRAM caches require a tag store of several tens of megabytes, commercial DRAM cache designs typically co-locate tag and data within the DRAM array. DRAM caches are organized as a direct-mapped structure so that the tag and data can be streamed out in a single access. While direct-mapped DRAM caches provide low hit-latency, they suffer from low hit-rate due to conflict misses. Ideally, we want the hit-rate of a set-associative DRAM cache, without incurring additional latency and bandwidth costs of increasing associativity. To address this problem, way prediction can be applied to a set-associative DRAM cache to achieve the latency and bandwidth of a direct-mapped DRAM cache. Unfortunately, conventional way prediction policies typically require per-set storage, causing multi-megabyte storage overheads for gigascale DRAM caches. If we can obtain accurate way prediction without incurring significant storage overheads, we can efficiently enable set-associativity for DRAM caches. This paper proposes Associativity via Coordinated Way-Install and Way-Prediction (ACCORD), a design that steers an incoming line to a "preferred way" based on the line address and uses the preferred way as the default way prediction. We propose two way-steering policies that are effective for 2-way caches. First, Probabilistic Way-Steering (PWS), which steers lines to a preferred way with high probability, while still allowing lines to be installed in an alternate way in case of conflicts. Second, Ganged Way-Steering (GWS), which steers lines of a spatially contiguous region to the way where an earlier line from that region was installed. On a 2-way cache, ACCORD (PWS+GWS) obtains a way prediction accuracy of 90% and retains a hit-rate similar to a baseline 2-way cache while incurring 320 bytes of storage overhead. We extend ACCORD to support highly-associative caches using a Skewed Way-Steering (SWS) design that steers a line to at-most two ways in the highly-associative cache. This design retains the low-latency of the 2-way ACCORD while obtaining most of the hit-rate benefits of a highly associative design. Our studies with a 4GB DRAM cache backed by non-volatile memory shows that ACCORD provides an average of 11% speedup (up to 54%) across a wide range of workloads.