Fast Data Delivery for Many-Core Processors
Fast Data Delivery for Many-Core Processors
复制标题
众核处理器的快速数据传输
DOI：
10.1109/tc.2018.2821144
复制
发表时间：
2018
影响因子：
3.7
通讯作者：
H. Sarbazi
中科院分区：
文献类型：
--
作者：
Mohammad Bakhshalipour;Pejman Lotfi;Abbas Mazloumi;Farid Samandi;Mahmood Naderan;M. Modarressi;H. Sarbazi
服务器工作负载处理大量数据。因此，执行这些工作负载的处理器频繁出现一级数据缓存（L1 - D）缺失。在多核处理器中，一级数据缓存缺失会导致请求数据包被发送到末级缓存（LLC）切片，并将响应数据包发送回一级数据缓存，这会产生高额开销。虽然先前的工作针对响应数据包，但这项工作侧重于加速请求数据包。与激进的乱序执行（OoO）内核不同，多核处理器中使用的较简单内核无法隐藏一级数据缓存请求数据包的延迟。我们观察到处理一级数据缓存缺失的末级缓存切片在时间上具有很强的相关性。利用这一观察结果，我们设计了一种简单而准确的预测器。当发生一级数据缓存缺失时，预测器会识别出将处理下一次一级数据缓存缺失的末级缓存切片，并为即将到来的缺失请求建立一条电路以加速其传输。当即将到来的缺失发生时，产生的请求可以使用已经建立的电路传输到末级缓存切片。我们表明，由于（1）更高的预测准确性和（2）不浪费宝贵的片外带宽，同时所需开销显著更低，我们的方案在多核处理器中优于数据预取机制。通过全系统模拟，我们表明我们的方案将处理数据缺失的速度提高了22%，并比最先进的片上网络性能提高了10%。
Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. In a many-core processor, an L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets. Unlike aggressive OoO cores, simpler cores used in many-core processors cannot hide the latency of L1-D request packets. We observe that LLC slices that serve L1-D misses are strongly temporally correlated. Taking advantage of this observation, we design a simple and accurate predictor. Upon the occurrence of an L1-D miss, the predictor identifies the LLC slice that will serve the next L1-D miss and a circuit will be set up for the upcoming miss request to accelerate its transmission. When the upcoming miss occurs, the resulting request can use the already established circuit for transmission to the LLC slice. We show that our proposal outperforms data prefetching mechanisms in a many-core processor due to (1) higher prediction accuracy and (2) not wasting valuable off-chip bandwidth, while requiring significantly less overhead. Using full-system simulation, we show that our proposal accelerates serving data misses by 22 percent and leads to 10 percent performance improvement over the state-of-the-art network-on-chip.