Analysis and avoidance of cross-talk in on-chip buses
Analysis and avoidance of cross-talk in on-chip buses
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DOI：
10.1109/his.2001.946705
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发表时间：
2001-08
期刊：
影响因子：
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通讯作者：
C. Duan;A. Tirumala;S. Khatri
中科院分区：
文献类型：
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作者：
C. Duan;A. Tirumala;S. Khatri
我们提出了分析和缓解片上总线中串扰的技术。随着工艺特征尺寸的迅速缩小，布线延迟正在成为电路总延迟的一大部分。此外，同一金属层上的导线之间的交叉耦合电容的增加造成了导线的延迟强烈依赖于其相邻导线的电气状态的情况。一条线路的延迟可能会有很大的差异，这取决于它的邻居是否执行类似的转换。这种影响对于长的片上总线来说非常严重。在这项工作中，我们对片上总线线间的串扰相互作用进行了分类。我们提出的编码技术可以帮助设计者在串扰和面积开销之间进行权衡。我们的实验结果表明，所提出的技术降低了由于串扰引起的时延变化。结果，即使在使用编码方案之后，总线的总延迟实际上也减少了。
We present techniques to analyze and alleviate cross-talk in on-chip buses. With rapidly shrinking process feature sizes, wire delay is becoming a large fraction of the overall delay of a circuit. Additionally, the increasing cross-coupling capacitances between wires on the same metal layer create a situation where the delay of a wire is strongly dependent on the electrical state of its neighboring wires. The delay of a wire can vary widely depending on whether its neighbors perform a like or unlike transition. This effect is acute for long on-chip buses. In this work, we classify cross-talk interactions between the wires of an on-chip bus. We present encoding techniques which can help a designer trade off cross-talk against area overhead. Our experimental results show that the proposed techniques result in reduced delay variation due to cross-talk. As a result, the overall delay of a bus actually decreases even after the use of the encoding scheme.