A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE
A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE
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用于将等离激元仿真应用程序迁移到 SX-ACE 的内存优化案例研究
DOI：
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发表时间：
2015
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通讯作者：
Hiroaki Kobayashi
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作者：
R. Mathur;Hiroshi Matsuoka;Osamu Watanabe;A. Musa;Ryusuke Egawa;Hiroaki Kobayashi
由于目前的科学和工程模拟需要大量的数据进行繁重的计算，因此高性能计算(HPC)系统需要高计算能力和大存储容量。目前的高性能计算系统大多采用并行处理体系结构，其中处理器的计算能力很高，但存储系统的性能受到限制。每个触发器的字节数(B/F)是存储器带宽与触发器/S的比率，以及高性能计算机系统的单个节点上的存储器容量随着高性能计算机系统的发展而减少。为了充分挖掘当前高性能计算系统的潜力，有必要优化实际的科学和工程应用，不仅要考虑应用程序的并行性，而且要考虑高性能计算系统存储系统的局限性。在本文中，我们讨论了一组优化应用程序的内存访问行为的方法，使它们能够在最近的高性能计算系统上以更高的性能执行。我们的方法包括通过内存占用控制进行内存优化，对活动元素进行内存重组，通过组合计算消除冗余数据结构，以及优化数据重新计算。为了验证这些方法的有效性，在NEC SX-ACE上实现了一个等离子体激元模拟应用程序。通过将我们的方法应用到实现中，对于小规模数据集，等离子体激元模拟应用程序的内存使用量可以从35.6 GB减少到512 MB，对于大规模数据集，可以从65.1 GB减少到4.3 GB，从而使其能够在内存容量较小的分布式并行系统的单个节点上执行。此外，性能评估表明，该优化算法的执行速度提高了1.14倍。
Since recent scientific and engineering simulations require heavy computations with large volumes of data, High-performance Computing (HPC) systems need a high computational capability with a large memory capacity. Most recent HPC systems adopt a parallel processing architecture, where the computational capability of the processors is high, but the performance of the memory system is constrained. The bytes per flop (B/F), which is a ratio of the memory bandwidth to the flop/s, and the memory capacity on a single node of the HPC systems have been reduced according to the evolution of the HPC systems. To fully exploit the potential of the recent HPC systems, it is necessary to optimize practical scientific and engineering applications, not only considering the parallelism of the applications, but also the limitations of the memory systems of the HPC systems. In this paper, we discuss a set of approaches to optimization of the memory access behavior of the applications, which enable their executions on the recent HPC systems with improved performance. Our approaches include memory optimization through memory footprint controlling, memory restructuring for active elements, redundant data-structure elimination through combined calculations and optimized re-calculation of data. To validate the effectiveness of our approaches, a plasmonics simulation application is implemented on NEC SX-ACE. By applying our approaches to the implementation, the memory usage of the plasmonics simulation application can be reduced from 35.6 GB to 512 MB for a small-scale dataset, and from 65.1 GB to 4.3 GB for a large-scale dataset, enabling its execution on a single node of a distributed parallel system with lesser memory capacity. Besides, the performance evaluation shows that the optimization achieves 1.14 times faster execution.