DeltaSyn: An efficient logic difference optimizer for ECO synthesis
DeltaSyn: An efficient logic difference optimizer for ECO synthesis
复制标题
DeltaSyn：用于 ECO 综合的高效逻辑差异优化器
DOI：
10.1145/1687399.1687546
复制
发表时间：
2009
期刊：
影响因子：
--
通讯作者：
R. Puri
中科院分区：
文献类型：
--
作者：
Smita Krishnaswamy;Haoxing Ren;Nilesh A. Modi;R. Puri
在IC设计过程中，功能规范在设计周期后期通常会在安置和路由完成后修改。但是，设计人员要么手动手动处理此类修改，要么从头开始重新启动设计过程 - 这是一个非常昂贵的选择。为了解决此问题，我们提出了Deltasyn，这是一种在修改后的高级规范和实现的设计之间生成高度优化的逻辑差异的方法。 Deltasyn具有在实现的逻辑中定位边界的能力，可以将更改限制在其中。 Delta-syn分为两个阶段将边界划定。第一阶段采用快速功能和结构分析技术来识别形成变化的输入侧边界的等效信号。第二阶段通过一种新型的动态算法定位变化的输出侧边界，该算法从ECO所需的变化中检测到下游匹配的逻辑。工业设计的实验表明，这些技术共同实施了ECO，同时平均保留了现有逻辑的97％。与以前的方法不同，位平行逻辑模拟和快速SAT求解器的使用可以实现高性能和可扩展性。 Deltasyn可以在约200秒或更短的时间内处理大约10K门的设计并验证典型的ECO。
During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design process from scratch - a very costly option. In order to address this issue, we present DeltaSyn, a method for generating a highly optimized logic difference between a modified high-level specification and an implemented design. DeltaSyn has the ability to locate boundaries in implemented logic within which changes can be confined. Delta-Syn demarcates the boundary in two phases. The first phase employs fast functional and structural analysis techniques to identify equivalent signals forming the input-side boundary of the changes. The second phase locates the output-side boundary of the changes through a novel dynamic algorithm that detects matching logic downstream from the changes required by the ECO. Experiments on industrial designs show that together these techniques successfully implement ECOs while preserving an average of 97% of the existing logic. Unlike previous approaches, the use of bit-parallel logic simulation and fast SAT solvers enables high performance and scalability. DeltaSyn can process and verify a typical ECO for a design of around 10K gates in about 200 seconds or less.