A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits
A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits
复制标题
单通量量子逻辑电路的变化感知保持时间固定方法
DOI：
10.1145/3460289
复制
发表时间：
2021
影响因子：
1.4
通讯作者：
Beerel, Peter A.
中科院分区：
文献类型：
--
作者：
Li, Xi;Shahsavani, Soheil Nazar;Zhou, Xuan;Pedram, Massoud;Beerel, Peter A.
单通量量子 (SFQ) 逻辑是一种很有前景的技术，可以在未来的百万兆级超级计算中取代互补金属氧化物半导体逻辑，但需要开发针对 SFQ 电路独特特性的可靠 EDA 工具，包括需要有源分路器来支持扇出和时钟逻辑门。本文是第一篇提出在 SFQ 电路中插入保持缓冲器的物理设计方法的著作。我们的方法是变化感知的，使用公共路径悲观消除和增量放置来最小化时序修复的开销，并且可以权衡布局面积和时序良率。与之前提出的使用固定保持时间裕度的方法相比，蒙特卡洛模拟表明，对 10 个 ISCAS’85 基准电路进行平均，我们提出的方法可以将插入的保持缓冲区数量减少 8.4%，时序良率提高 6.2%，时序良率提高 1.7%，插入保持缓冲区数量减少 21.9%。
Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, usescommon path pessimism removaland incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.
RSFQ 异步方法的回顾和比较
DOI：
--
发表时间：
2008
期刊：
影响因子：
--
作者：
L. C. Muller;H. R. Gerber;C. Fourie
通讯作者：
C. Fourie