Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI
Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI
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电源电压对半微米及以下亚微米 CMOS LSI 电路性能的影响
DOI：
10.1109/16.57142
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发表时间：
1990
期刊：
影响因子：
--
通讯作者：
M. Kinugawa
中科院分区：
文献类型：
--
作者：
M. Kakumu;M. Kinugawa
基于理论认识，引入了电源电压下限可简单表示为1.1E/sub c/L/sub eff/的概念，其中E/sub c/为引起载流子速度饱和所需的临界电场，L/sub eff/为有效沟道长度。实验结果证实，1.1E/sub c/L/sub eff/预测的电源电压的CMOS器件在宽范围的栅氧化层厚度（7-45 nm）和设计规则（0.3-2.0 μ m）的一个很好的指南。在理论模型和实验结果的基础上，分析了电源电压随MOS器件尺寸的变化趋势。它示出，1.1E/sub c/L/sub eff/可以被视为电源电压的下限，以保持低于0.6 μ m的沟道长度在降低电源的延迟时间的改善。为了解释1.1E/sub c/L/sub eff/的物理意义，研究了MOSFET在高电场下的击穿行为。>
Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is the effective channel length, is introduced. Experimental results confirmed that 1.1E/sub c/L/sub eff/ predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 mu m). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E/sub c/L/sub eff/ can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6- mu m channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E/sub c/L/sub eff/. >