Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance
Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance
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DOI：
10.1109/tc.2012.60
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发表时间：
2013-06
影响因子：
3.7
通讯作者：
Yang Hu;Hong Jiang;D. Feng;Lei Tian;Hao Luo;Chao Ren
中科院分区：
文献类型：
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作者：
Yang Hu;Hong Jiang;D. Feng;Lei Tian;Hao Luo;Chao Ren
考虑到SSD内部并行性在通道级、芯片级、管芯级和平面级这四个不同级别上的多级性，如何利用这些级别的并行性将直接且显著地影响SSD的性能和耐久性，而这又主要由三个内部因素决定，即高级命令、分配方案和利用四个级别的并行性的优先顺序。在本文中，我们分析这些内部因素，以表征其影响，相互作用和并行性的目的，通过深入的实验研究的SSD的性能和耐久性增强。我们得出以下关键结论：1）闪存制造商提供的不同高级命令利用SSD内部不同级别的并行性，根据使用方式，它们可以提高或降低SSD的性能和耐用性; 2）不同的物理页面分配方案采用不同的高级命令，并利用SSD内部的不同级别的并行性，3）在三个内部因素中，使用四个并行级别的优先顺序对性能和耐久性的影响最显著。在SSD中使用四个级别的并行性的最佳优先级顺序被发现是：1）通道级并行性; 2）管芯级并行性; 3）平面级并行性;以及4）芯片级并行性。
Given the multilevel internal SSD parallelism at the different four levels: channel-level, chip-level, die-level, and plane-level, how to exploit these levels of parallelism will directly and significantly impact the performance and endurance of SSDs, which is in turn primarily determined by three internal factors, namely, advanced commands, allocation schemes, and the priority order of exploiting the four levels of parallelism. In this paper, we analyze these internal factors to characterize their impacts, interplay, and parallelism for the purpose of performance and endurance enhancement of SSDs through an in-depth experimental study. We come to the following key conclusions: 1) Different advanced commands provided by Flash manufacturers exploit different levels of parallelism inside SSDs, where they can either improve or degrade the SSD performance and endurance depending on how they are used; 2) Different physical-page allocation schemes employ different advanced commands and exploit different levels of parallelism inside SSDs, giving rise to different performance and endurance impacts; 3) The priority order of using the four levels of parallelism has the most significant performance and endurance impact among the three internal factors. The optimal priority order of using the four levels of parallelism in SSDs is found to be: 1) the channel-level parallelism; 2) the die-level parallelism; 3) the plane-level parallelism; and 4) the chip-level parallelism.