Reconfiguration in FPGA-based multi-core platforms for hard real-time applications
Reconfiguration in FPGA-based multi-core platforms for hard real-time applications
复制标题
基于 FPGA 的多核平台中针对硬实时应用的重新配置
DOI：
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发表时间：
2016
期刊：
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通讯作者：
J. Sparsø
中科院分区：
文献类型：
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作者：
Luca Pezzarossa;Martin Schoeberl;J. Sparsø
在通用计算多核平台中，硬件加速器和重构是提高性能的手段；例如，软件应用程序的平均执行时间。在硬实时系统中，这种平均情况下的加速本身无关紧要——决定系统及时响应能力的是应用程序任务的最坏情况执行时间。为了支持这一重点，平台必须为通信和计算资源提供服务保障。此外，许多硬实时应用具有多种操作模式，每种模式都有特定的要求。关于可重构计算的一个有趣的观点是利用运行时重构来支持模式更改。本文探讨了T-CREST硬实时多核平台中通信和计算资源重构的方法。通过扩展具有设置、拆除和修改虚拟电路带宽功能的消息传递片上网络来支持通信资源的重新配置。计算资源的重新配置，如硬件加速器，是使用现代fpga中发现的动态部分重新配置能力来执行的。
In general-purpose computing multi-core platforms, hardware accelerators and reconfiguration are means to improve performance; i.e., the average-case execution time of a software application. In hard real-time systems, such average-case speed-up is not in itself relevant - it is the worst-case execution-time of tasks of an application that determines the systems ability to respond in time. To support this focus, the platform must provide service guarantees for both communication and computation resources. In addition, many hard real-time applications have multiple modes of operation, and each mode has specific requirements. An interesting perspective on reconfigurable computing is to exploit run-time reconfiguration to support mode changes. In this paper we explore approaches to reconfiguration of communication and computation resources in the T-CREST hard real-time multi-core platform. The reconfiguration of communication resources is supported by extending the message-passing network-on-chip with capabilities for setting up, tearing down, and modifying the bandwidth of virtual circuits. The reconfiguration of computation resources, such as hardware accelerators, is performed using the dynamic partial reconfiguration capabilities found in modern FPGAs.