ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators
ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators
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DOI：
10.1145/3579371.3589076
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发表时间：
2023-04
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影响因子：
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通讯作者：
Nisarg Ujjainkar;Jingwen Leng;Yuhao Zhu
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文献类型：
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作者：
Nisarg Ujjainkar;Jingwen Leng;Yuhao Zhu
图像处理算法是硬件加速度的主要目标，因为它们通常用于资源和功率有限的应用程序中。当今的图像处理加速器设计对算法结构和/或片上内存资源进行了严格的假设。结果，它们要么具有狭窄的适用性或导致设计效率低下。本文提出了一个编译器框架，该框架会自动生成内存和功率效率的图像处理加速器。我们允许程序员描述通用图像处理算法（以域特定的语言），并指定可用的芯片内存结构。然后，我们的框架制定了一个受约束的优化问题，该问题可以最大程度地减少芯片内存储器的使用情况，同时保持理论最大吞吐量。我们要解决的主要挑战是分析表达吞吐量瓶颈，即芯片内存的争夺，以实现轻量级的汇编。 FPGA原型制作和ASIC综合表明，与现有方法相比，我们的框架生成的加速器减少了芯片内存的使用和/或功率消耗。成像代码可在以下网址获得：https：//github.com/horizon-research/imagen。
Image processing algorithms are prime targets for hardware acceleration as they are commonly used in resource- and power-limited applications. Today's image processing accelerator designs make rigid assumptions about the algorithm structures and/or on-chip memory resources. As a result, they either have narrow applicability or result in inefficient designs. This paper presents a compiler framework that automatically generates memory- and power-efficient image processing accelerators. We allow programmers to describe generic image processing algorithms (in a domain specific language) and specify on-chip memory structures available. Our framework then formulates a constrained optimization problem that minimizes on-chip memory usage while maintaining theoretical maximum throughput. The key challenge we address is to analytically express the throughput bottleneck, on-chip memory contention, to enable a lightweight compilation. FPGA prototyping and ASIC synthesis show that, compared to existing approaches, accelerators generated by our framework reduce the on-chip memory usage and/or power consumption by double digits. ImaGen code is available at: https://github.com/horizon-research/imagen.