A fast, energy efficient, field programmable threshold-logic array
A fast, energy efficient, field programmable threshold-logic array
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快速、节能、现场可编程阈值逻辑阵列
DOI：
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发表时间：
2014
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通讯作者：
S. Vrudhula
中科院分区：
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作者：
Niranjan S. Kulkarni;Jinghua Yang;S. Vrudhula
与传统的and /OR逻辑等效物[1]相比，阈值逻辑门长期以来一直被认为可以产生更紧凑和更快的电路，然而，由于缺乏高效可靠的门实现以及自动化合成和物理设计所需的基础设施，基于阈值逻辑的设计尚未进入主流设计技术（既不是定制ASIC也不是FPGA）。本文是解决这一差距的一步。我们提出了一种新型可编程逻辑阵列的架构，称为现场可编程阈值逻辑阵列（FPTLA），其中基本单元是差分模式阈值逻辑门（dtg）。每个单独的DTG单元是一个时钟边缘触发电路，计算一个阈值逻辑函数。可以对DTG进行编程，通过将适当的信号路由到其输入端来实现不同的阈值逻辑功能。与传统的clb相比，这将逻辑块内的sram数量减少了大约60%，而不会在路由基础设施中增加任何显著的开销。由于DTG本质上是一个计算阈值函数的多输入、边缘触发触发器，因此DTG网络形成了纳米流水线电路。采用成熟的FPGA设计框架VTR （Verilog To Routing）和VPR (Versatile Place and Route)[2]，在FPTLAs和传统FPGA上实现了一组深度流水线数据路径电路，证明了这种网络的优势。结果表明，与传统的基于LUT的FPGA相比，在几乎相同的能量和逻辑面积下，FPGA可以实现高达2倍的延迟改进。虽然差模电路可能对工艺变化更敏感，但fptla可以在不牺牲其提高的能效和性能的情况下对这种变化进行鲁棒化。
Threshold-logic gates have long been known to result in more compact and faster circuits when compared to conventional AND/OR logic equivalents [1], However, threshold logic based design has not entered the mainstream design technology (neither custom ASIC nor FPGA) due to the lack of efficient and reliable gate implementations and the necessary infrastructure for automated synthesis and physical design. This paper is a step toward addressing this gap. We present the architecture of a novel programmable logic array, referred to as Field Programmable Threshold-Logic Array (FPTLA), in which the basic cells are differential mode threshold-logic gates (DTGs). Each individual DTG cell is a clock edge-triggered circuit that computes a threshold-logic function. A DTG can be programmed to implement different threshold logic functions by routing appropriate signals to their inputs. This reduces the number of SRAMs inside the logic blocks by about 60% compared to conventional CLBs, without adding any significant overhead in the routing infrastructure. Since a DTG is essentially a multi-input, edge-triggered flipflop that computes a threshold function, a network of DTGs forms a nano-pipelined circuit. The advantages of such a network are demonstrated on a set of deeply pipelined datapath circuits implemented on FPTLAs and conventional FPGAs using the well established FPGA design framework VTR (Verilog To Routing) and VPR (Versatile Place and Route) [2]. The results indicate that an FPTLA can achieve up to 2X improvement in delay for nearly the same energy and logic area compared to the conventional LUT based FPGA. Although differential mode circuits can potentially be more sensitive to process variations, FPTLAs can be made robust to such variations without sacrificing their improved energy efficiency and performance over FPGAs.