Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations
Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations
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DOI：
10.1109/iedm.2013.6724744
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发表时间：
2013-12
期刊：
影响因子：
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通讯作者：
U. Avci;D. Morris;S. Hasan;R. Kotlyar;Raseong Kim;R. Rios;D. Nikonov;I. Young
中科院分区：
文献类型：
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作者：
U. Avci;D. Morris;S. Hasan;R. Kotlyar;Raseong Kim;R. Rios;D. Nikonov;I. Young
降低电源电压（VDD）同时保持低漏电流对于最小化能耗和提高移动终端电池寿命至关重要。MOSFET亚阈值斜率（SS）的热极限限制了阈值电压（Vt）的降低，导致低导通电阻下的性能显著下降。Tunnel Field Effect Transistor（TFET）不受该热尾的限制，并且在低介电常数下可以表现得更好[1，2]。在本文中，一个领先的N-TFET选项- GaSb/InAs异质结-是原子建模[3，4]和电路模拟模型的开发，预测64%的平均节能硅CMOS在Lg= 13纳米的纳米线。如果没有一个好的P-TFET选项，能源节省减少到21%。MOSFET和TFET器件的变化都受功函数变化的影响，当考虑变化时，TFET的节能略有减少。
Reducing supply voltage (Vdd) while keeping leakage current low is critical for minimizing energy consumption and improving mobile device battery life. The thermal limit of MOSFET subthreshold slope (SS) restricts lowering threshold voltage (Vt), causing significant performance degradation at low Vdd. A Tunneling Field Effect Transistor (TFET) is not limited by this thermal tail and may perform better at low Vdd [1,2]. In this paper, a leading N-TFET option - GaSb/InAs heterojunction - is atomistically modeled [3,4] and circuit simulation models are developed to predict 64% average energy savings against Si CMOS at Lg=13nm for a nanowire. Energy savings diminish to 21% without a good P-TFET option. Both MOSFET and TFET device variations are dominated by work-function variation, and TFET energy savings are slightly reduced when variations are considered.