Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
复制标题
平均功率约束下嵌入式内核的多频包装设计和优化
DOI：
10.1145/1065579.1065615
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
K. Chakrabarty
中科院分区：
文献类型：
--
作者：
Q. Xu;N. Nicolici;K. Chakrabarty
本文提出了一种为具有多个时钟域的嵌入式内核设计测试包装器的新方法。通过利用多个移位频率，所提出的方法改进了最近的包装器设计方法，该方法需要不同时钟域中的扫描元件的公共移位频率。作者提出了一种整数线性规划（ILP）模型，可用于最大限度地减少小问题实例的测试时间。还提出了一种有效的启发式方法，适用于大型问题实例，并且对于小问题实例产生与 ILP 相同的（最佳）测试时间。与最近使用单移频进行包装器设计的工作相比，获得了更短的测试时间，并且在功率限制下测试时间的减少尤其显着。
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. The authors presented an integer linear programming (ILP) model that could be used to minimize the testing time for small problem instances. An efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances was also presented. Compared to recent work on wrapper design using a single shift frequency, lower testing times were obtained and the reduction in testing time is especially significant under power constraints.