Issue Mechanism for Embedded Simultaneous Multithreading Processor
Issue Mechanism for Embedded Simultaneous Multithreading Processor
复制标题
DOI：
10.1093/ietfec/e91-a.4.1092
复制
发表时间：
2008-04
期刊：
影响因子：
--
通讯作者：
C. Zang;S. Imai;S. Frank;S. Kimura
中科院分区：
文献类型：
--
作者：
C. Zang;S. Imai;S. Frank;S. Kimura
同步多线程（SMT）技术通过在一个时钟周期内从多个线程发出多条指令来提高指令吞吐量。对于每个线程的有序管道，SMT处理器可以提供接近或超过无序管道的大量发出指令。在这项工作中，我们展示了一种有效的问题逻辑，用于每个指令中带有并行标志的谓词指令序列，其中采用基于谓词寄存器的问题控制，并行执行带有并行标志“0”的连续指令。该标志是由编译器预先定义的。来自不同线程的指令根据循环顺序发出。我们还为线程引入了指令队列跳过机制，如果队列是空的。利用这种问题逻辑，我们设计了一个6线程、7阶段的顺序流水线处理器。基于这个处理器，我们将循环发布策略（RR(T1- tn)）与其他策略进行比较：线程1始终具有最高优先级（PR(T1)），线程1或线程n依次具有最高优先级（PR(T1- tn)）。结果表明，从每个周期发出的指令来看，RR（T1-Tn）政策优于其他政策，PR（T1-Tn）与RR（T1-Tn）几乎相同。
Simultaneous Multithreading (SMT) technology enhances instruction throughput by issuing multiple instructions from multiple threads within one clock cycle. For in-order pipeline to each thread, SMT processors can provide large number of issued instructions close to or surpass than using out-of-order pipeline. In this work, we show an efficient issue logic for predicated instruction sequence with the parallel flag in each instruction, where the predicate register based issue control is adopted and the continuous instructions with the parallel flag of '0' are executed in parallel. The flag is pre-defined by a compiler. Instructions from different threads are issued based on the round-robin order. We also introduce an Instruction Queue skip mechanism for thread if the queue is empty. Using this kind of issue logic, we designed a 6 threads, 7-stage, in-order pipeline processor. Based on this processor, we compare round-robin issue policy (RR(T1-Tn)) with other policies: thread one always has the highest priority (PR(T1)) and thread one or thread n has the highest priority in turn (PR(T1-Tn)). The results show that RR(T1-Tn) policy outperforms others and PR(T1-Tn) is almost the same to RR(T1-Tn) from the point of view of the issued instructions per cycle.