MOS interface control technologies for III-V/Ge channel MOSFETs
MOS interface control technologies for III-V/Ge channel MOSFETs
复制标题
III-V/Ge 通道 MOSFET 的 MOS 接口控制技术
DOI：
10.1149/1.3633015
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
T.Hoshii and M.Takenaka
中科院分区：
文献类型：
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作者：
S.Takagi;R.Zhang;T.Hoshii and M.Takenaka
使用具有低有效质量的沟道材料的MOSFET对于在亚10 nm范围下获得高电流驱动和低电源电压CMOS已经被认为是非常重要的。从这一观点出发，最近已经将注意力放在III-V和Ge沟道上。然而，实现Ge/III-V MOSFET最关键的问题之一是在Ge/III-V上形成具有上级MOS界面质量的栅极绝缘体。在本文中，我们专注于Ge/III-V上的栅极堆叠技术的可能解决方案。对于Ge，GeO 2/Ge界面被认为是有前途的。然而，这些界面仍然采用厚的GeO 2层。最近，我们已经成功地在薄EOT栅堆叠与锗氧化物界面层，使用ECR等离子体后氧化。通过将ALD Al_2O_3/Ge结构暴露于ECR氧等离子体并通过非常薄的ALD Al_2O_3层氧化Ge表面来制造高质量的Al_2O_3/GeOx/Ge栅堆叠。我们提出了我们最近的结果，使用这个接口的接口属性。对于InGaAs沟道，我们也提出了一种新的界面控制技术，利用ECR氮等离子体InGaAs表面氮化和连续的金属化后退火。该界面层结合ECR溅射SiO2或ALD Al 2 O3栅极绝缘体被示出为减少Dit低至10 - 11 cm-2 eV-1的低阶。讨论了这一Dit还原的物理起源和氮化的作用。
MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO2/Ge interfaces have been regarded as promising. However, these interfaces have still employed thick GeO2 layers. Recently, we have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al2O3/GeOx/Ge gate stacks were fabricated by exposing the ALD Al2O3/Ge structures to ECR oxygen plasma and oxidizing the Ge surface through the very thin ALD Al2O3 layer. We present our recent results of the interface properties using this interface. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer combined with an ECR sputtering SiO2 or an ALD Al2O3 gate insulator is shown to reduce Dit down to low order of 10 11 cm-2 eV-1. The physical origin of this Dit reduction and the role of the nitridation are discussed.