Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors
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基于双栅极可控极性晶体管的功率门控差分逻辑类型
DOI：
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发表时间：
2013
期刊：
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通讯作者：
G. Micheli
中科院分区：
文献类型：
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作者：
L. Amarù;P. Gaillardon;Jian Zhang;G. Micheli
本文提出了一种基于双栅极（DG）可换极性场效应管（FET）的差分级联电压开关逻辑（DCVSL）的新型功率门控技术。DG可换极性FET，通常称为双极晶体管，是其极性可通过改变第二栅极偏置在线重新配置的器件。在这个简短的，我们利用双极器件极性的在线控制，以实现本征功率门控DCVSL电路绕过使用串联睡眠晶体管。我们在22纳米技术节点进行电路级仿真和比较，考虑硅纳米线为基础的DG可换极性场效应管。实验结果表明，采用该技术的双极性DCVSL电路的待机功耗平均是非功率门控电路的6倍，而时序代价仅为非功率门控电路的1.1倍。与基于单极FinFET的实现相比，我们的建议能够降低低待机功耗工艺的待机功耗高达1.9倍，同时，提高高性能工艺的性能高达10%。
This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar transistors, are devices whose polarity is online reconfigurable by changing the second gate bias. In this brief, we exploit the online control of ambipolar device polarity to achieve intrinsically power-gated DCVSL circuits bypassing the use of series sleep transistors. We perform circuit-level simulations and comparisons at 22-nm technology node, considering silicon nanowire -based DG controllable-polarity FETs. Experimental results show that ambipolar DCVSL circuits power gated by the proposed technique have on average 6× smaller standby power with only 1.1× timing penalty with respect to their non-power-gated versions. As compared with unipolar FinFET-based realizations, our proposal is capable to reduce up to 1.9× the standby power consumption of a low-standby-power process and, at the same time, increase up to 10% the performance of a high-performance process.