Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability
Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability
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用于可靠性模拟设计的 MOS 晶体管热载流子退化分析建模
DOI：
10.1109/isqed.2007.37
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
F. Braun
中科院分区：
文献类型：
--
作者：
Benoit Dubois;J. Kammerer;L. Hébrard;F. Braun
本文提出了一种CMOS三极管老化分析模型，并给出了提取其参数的方法。通过一个简单的例子，我们进一步说明了如何使用这种模型来预测一个电路的主要特性的漂移，我们还证明了这个模型也可以用来帮助设计者选择和/或修改电路，以使热载流子引起的退化最小化。文中还给出了仿真结果与分析结果的比较
A CMOS transistor ageing analytical model is presented and the procedure that allows to extract its parameters is proposed in this paper. By using a simple, example, we show how such a model can be used to forecast the drifts of the main characteristics of a CMOS circuit Further, we demonstrate that this model can also be used to help the designer to choose and/or modify a circuit in order to minimize the hot-carrier induced degradations. Simulation results compared to the analytical study are also shown