A 40-ns 17-Bit by 17-Bit Array Multiplier
A 40-ns 17-Bit by 17-Bit Array Multiplier
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40ns 17 位 x 17 位阵列乘法器
DOI：
10.1109/t-c.1971.223261
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发表时间：
1971
影响因子：
3.7
通讯作者：
S. Pezaris
中科院分区：
文献类型：
--
作者：
S. Pezaris
描述了一种高速阵列乘法器，可在 40 ns 内生成两个 17 位有符号（2 的补码）数的完整 34 位乘积。该乘法器使用带有预期进位的特殊 2 位门控加法器电路。处理负数时，将其最高位视为负数，将所有其他位视为正数，并通过适当的电路直接添加负部分积。和信号与进位信号的传播使得和延迟不会显着影响整个乘法器延迟。
A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with anticipated carry. Negative numbers are handled by considering their highest order bit as negative, all other bits as positive, and adding negative partial products directly through appropriate circuits. The propagation of sum and carry signals is such that sum delays do not significantly contribute to the overall multiplier delay.