Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications
Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications
复制标题
DOI：
10.1109/ted.2015.2389900
复制
发表时间：
2015-01
影响因子：
3.1
通讯作者：
Chitrakant Sahu;Jawar Singh
中科院分区：
文献类型：
--
作者：
Chitrakant Sahu;Jawar Singh
在本文中，我们报告了无掺杂的双栅场效应晶体管（DL-DGFET）的低功耗应用的潜在好处，设计在绝缘体上的单晶硅薄膜。模拟结果表明，与高掺杂无结（JL）DGFET相比，该器件具有更高的导通电流和对器件参数变化更小的敏感性。在DL-DGFET中使用中间带隙材料作为栅电极，也放松了JL器件的高金属栅功函数的约束。灵敏度分析表明，由于抑制了短沟道效应，DL-DGFET对器件参数变化，特别是栅长变化的灵敏度最小。DL-DGFET在关断状态下具有较低的静态功耗，在导通状态下具有较低的本征延迟。采用DL-DGFET的6 T静态随机存取存储器单元的混合模式仿真显示，在VDD = 0.8 V时，超低功耗应用的读取和保持噪声容限分别为147 mV和352 mV。最后提出了DL-DGFET的制作工艺流程。
In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at VDD = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.