DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework
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DOI：
10.2197/ipsjtsldm.8.63
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
Matthias Jung;C. Weis;N. Wehn
中科院分区：
文献类型：
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作者：
Matthias Jung;C. Weis;N. Wehn
在从移动设备到服务器的系统中，动态随机存取存储器 (DRAM) 对性能有很大影响，并且占总功耗的很大一部分。基于 DDR3 的传统解决方案捉襟见肘，因为它们的最大带宽受到 I/O 数量和接口速度的限制。随着新的解决方案不断上市（JEDEC DDR4、JEDEC WIDE I/O、美光的混合内存立方体：HMC 或 JEDEC 的高带宽内存：HBM），评估这些解决方案的性能并评估其对特定应用的适用性至关重要。此外，在具有 3D 堆叠的系统中，高功率密度和散热的挑战更加严峻。拥有灵活且全面的 DRAM 子系统框架对于详尽的设计空间探索至关重要，它可以处理所有不同类型的存储器以及性能、功耗和温度方面的问题。
In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes a significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by the I/O count and interface speed. As new solutions are coming onto the market (JEDEC DDR4, JEDEC WIDE I/O, Micron’s hybrid memory cube: HMC or JEDEC’s high bandwidth memory: HBM) it is critical to evaluate the performance of these solutions and assess their suitability for specific applications. Furthermore, in systems with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. It is crucial to have a flexible and holistic DRAM subsystem framework for exhaustive design space explorations, which can handle all this different types of memories, as well as the aspects of performance, power and temperature.