Placement Strategies for 2.5D FPGA Fabric Architectures
Placement Strategies for 2.5D FPGA Fabric Architectures
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2.5D FPGA 结构架构的布局策略
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
T. Bauer
中科院分区：
文献类型：
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作者：
C. Ravishankar;D. Gaitonde;T. Bauer
现场可编程门阵列（FPGAs）利用2.5D堆叠技术以合理的成本制造大容量和高性能的异构器件。电子设计自动化（EDA）工具需要了解并利用此类器件的物理特性，例如，超级逻辑区域（SLRs）之间连接数量的减少、结构中串行链路层（SLL）通道出现的频率较低以及单个超级逻辑区域的宽高比。我们实现了一种分区驱动的布局器，以探索各种EDA选项，从而利用2.5D FPGAs的架构特性。我们通过针对离散的串行链路层通道和减少的连接数量对布局器进行优化，提高了设计的可布线性。我们为分区器提出了一种切割调度方案，使其在了解超级逻辑区域宽高比的情况下确定布局方向，以改善每个超级逻辑区域内的布线通道需求。
FPGAs take advantage of 2.5D stacking technology to manufacture large capacity and high performance heterogenous devices at reasonable costs. EDA tools need to be aware of and exploit physical characteristics of such devices, for example the reduced connection count between SLRs, the infrequency of SLL channel occurence in the fabric, and the aspect ratios of individual SLRs. We implement a partition driven placer to explore various EDA options to take advantage of architectural features in 2.5D FPGAs. We improve the routability of designs by optimizing the placer for discrete SLL channels and reduced connection counts. We propose a cut schedule for the partitioner to orient the placement with awareness of the aspect ratio of SLRs to improve track demands within each SLR.