Interactions of Technology and Design in Nanoscale SRAM
Interactions of Technology and Design in Nanoscale SRAM
复制标题
纳米级 SRAM 中技术与设计的相互作用
DOI：
--
复制
发表时间：
2009
期刊：
影响因子：
--
通讯作者：
R. Mann
中科院分区：
文献类型：
--
作者：
R. Mann
硅技术的持续进步使VLSI工业能够将晶体管的面积缩小大约两倍，每个后续的技术节点。这一趋势持续了五十年，并使计算成为现代文化中无处不在的实体。由于CMOS技术的不断进步和日益增长的激烈竞争市场的推动，为了继续通过下一个十年，将需要CMOS工艺技术的持续进步以及电路设计创新。6T SRAM单元设计已经成功地在批量和SOI上缩小到32/28nm节点，并且在十多年来一直是先进CMOS技术的主导技术开发工具。随着技术规模的扩大，设备尺寸的减小和工作电压的降低导致了每个后续技术节点的设计挑战的增加。因此，降低的功能产率边际加上CMOS器件特性的可变性增加，已成为未来纳米级SRAM面临的最重要问题，激发了这一努力。为了应对这些挑战，该方法首先开发了一个基于定制尺度（90nm-22nm）的预测技术模型（PTM）框架，并使用公布的行业目标值进行校准，以量化和解决65nm以下节点的纳米SRAM面临的挑战。利用计算机辅助设计（TCAD）工具提出了6T单元设计拓扑在寻址变化中的作用和贡献。虽然电路辅助方法在延长6T SRAM寿命方面显示出希望，但本工作建议量化并开发一种基于灵敏度的方法，以评估辅助方法在解决功能边际减少方面的有效性。此外，提出了一种新的裕度/延迟分析作为评估电路辅助方法功能有效性的手段。余量/延迟分析可以进一步扩展，以评估电路辅助方法在将6T SRAM扩展到32nm节点以上时的局限性。最后，提出了一个基于约束的分析，以评估这些方法在多大程度上可以提供有效的解决方案，因为这些技术的规模超过32/28nm节点。
Continued advances in silicon technology have enabled the VLSI industry to shrink the area of the transistor by roughly a factor of two with each successive technology node. This trend has continued unabated for five decades and has made computing a ubiquitous entity in modern culture. Made possible by continuous advances in CMOS technology and fueled by a growing and fiercely competitive market, in order to continue through the next decade will require continued advances in CMOS process technology as well as circuit design innovation. The 6T SRAM cell design has been successfully scaled in both bulk and SOI down to the 32/28nm node and has remained for more than a decade the dominant technology development vehicle for advanced CMOS technologies. Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Thus, reduced functional yield margins coupled with increasing variability of the CMOS device characteristics have become the most significant problem facing future nanoscale SRAM, motivating this effort. To address these challenges, the proposed approach first develops a custom scaled (90nm-22nm) predictive technology model (PTM) based framework, calibrated using published industry target values to quantify and address the challenges confronting nanoscale SRAM below the 65nm node. The role and contribution of the 6T cell design topology in addressing variation is proposed using technology computer aided design (TCAD) tools. While circuit assist methods have shown promise in extending the life of the 6T SRAM, this work proposes to quantify and also develop a sensitivity based methodology for assessing the effectiveness of the assist methods in addressing the reduced functional margins. Additionally, a new margin/delay analysis is proposed as a means of assessing the functional effectiveness of the circuit assist methods. The margin/delay analysis may be further extended to assess the limits of circuit assist methods in extending the 6T SRAM beyond 32nm node. Finally, a constraint based analysis is proposed to assess the extent to which these methods may provide effective solutions as the technologies are scaled beyond the 32/28nm node.