An FPGA-based scalable simulation accelerator for tile architectures
An FPGA-based scalable simulation accelerator for tile architectures
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DOI：
10.1145/2082156.2082166
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发表时间：
2011-12
期刊：
影响因子：
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通讯作者：
Shinya Takamaeda-Yamazaki;Ryosuke Sasakawa;Yoshito Sakaguchi;Kenji Kise
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文献类型：
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作者：
Shinya Takamaeda-Yamazaki;Ryosuke Sasakawa;Yoshito Sakaguchi;Kenji Kise
基于现场可编程门阵列的仿真系统可以实时模拟处理器的行为。为了实际模拟多核体系结构，我们提出了使用多个现场可编程门阵列进行原型系统开发的ScalableCore。本文提出了一种基于现场可编程门阵列的可扩展核心系统1.1平台，该平台由多个名为可伸缩核心单元的模拟瓦片组成。每个瓷砖通过称为ScalableCore板的接口板连接到四个相邻瓷砖，因此增加目标核心数量很容易。文中还介绍了在FPGA上实现高可伸缩性仿真和实现复杂硬件功能的实用技术。开发的系统通过DMA通信和NoC来模拟磁砖体系结构的行为，速度是在配备Intel Core2Duo处理器的标准计算机上运行的相应的基于软件的功能模拟器的14.2倍。通过在基于软件的模拟器上比较模拟行为，验证了ScalableCore系统的周期准确性。
FPGA-based simulation systems can simulate processor behavior in realistic time. In order to practically simulate tile many-core architectures, we propose ScalableCore for prototyping system development using multiple FPGAs. In this paper, we present an FPGA-based platform called ScalableCore system 1.1, which consists of several simulation tiles named ScalableCore Units. Each tile is connected to four neighbor tiles via interface boards called ScalableCore Boards, and so increasing the target number of cores is easy. We also describe useful techniques by which to achieve high scalability of simulation and to implement complicated hardware functions on an FPGA. The developed system simulates the behavior of a tile architecture with DMA communications and NoC 14.2 times faster than a corresponding software-based functional simulator running on a standard computer with an Intel Core2Duo processor. We verified that the ScalableCore system is cycle-accurate by comparing the simulation behavior on a software-based simulator.