CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing

CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing
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DOI:
10.1145/3380446.3430633
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发表时间:
2020-11
期刊:
2020 ACM/IEEE 2nd Workshop on Machine Learning for CAD (MLCAD)
影响因子:
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通讯作者:
Zhengfeng Wu;I. Savidis
Zhengfeng Wu;I. Savidis
中科院分区:
其他
文献类型:
--
作者:
Zhengfeng Wu;I. Savidis

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开发了一种新的基于仿真的框架,该框架应用分类和自适应标记阈值(CALT)来自动生成模拟集成电路的元件尺寸。分类器用于预测是否满足目标规范。为了解决由于参数空间的大维度而缺乏具有正标签的数据点的问题,将标签阈值自适应地设置为给定电路性能度量在数据集中的分布的某个百分位数。执行随机森林分类器以用于代理预测建模,该代理预测建模提供设计参数的排名。对于模拟循环的每次迭代,利用优化来确定新的查询点。将CALT用于65 nm工艺低噪声放大器(LNA)的设计。为两套规范生成合格的设计方案,优化循环平均执行4次和17次,平均需要1287个和2190个模拟样本,平均执行时间分别为5.4小时和23.2小时。CALT是一个规范驱动的设计框架,可自动调整组件(晶体管、电容器、电感等)的大小。一种模拟电路。CALT生成可解释的模型并实现高采样效率,而不需要使用先前的电路模型。
A novel simulation-based framework that applies classification with adaptive labeling thresholds (CALT) is developed that auto-generates the component sizes of an analog integrated circuit. Classifiers are applied to predict whether the target specifications are satisfied. To address the lack of data points with positive labels due to the large dimensionality of the parameter space, the labeling threshold is adaptively set to a certain percentile of the distribution of a given circuit performance metric in the dataset. Random forest classifiers are executed for surrogate prediction modeling that provide a ranking of the design parameters. For each iteration of the simulation loop, optimization is utilized to determine new query points. CALT is applied to the design of a low noise amplifier (LNA) in a 65 nm technology. Qualified design solutions are generated for two sets of specifications with an average execution of 4 and 17 iterations of the optimization loop, which require an average of 1287 and 2190 simulation samples, and an average execution time of 5.4 hours and 23.2 hours, respectively. CALT is a specification-driven design framework to automate the sizing of the components (transistors, capacitors, inductors, etc.) of an analog circuit. CALT generates interpretable models and achieves high sample efficiency without requiring the use of prior circuit models.