A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
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DOI：
10.1109/jssc.2015.2453332
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发表时间：
2015-10-01
影响因子：
5.4
通讯作者：
Flynn, Michael P.
中科院分区：
文献类型：
--
作者：
Lim, Yong;Flynn, Michael P.
环形放大器是开关电容电路中OTA的一种高能效、高输出摆幅替代方案。然而，传统的环形放大器需要外部偏置，当我们考虑工艺、电源电压和温度（PVT）变化时，这使得环形放大器不太实用。本文提出了一种自偏置环形放大器方案，该方案使环形放大器更实用、更省电，同时保持了高效压摆充电和几乎轨到轨输出摆幅的优势。本文提出了一种改进的自调零方案，消除了自调零开关寄生电容引起的增益误差。此外，无比较器的流水线ADC结构利用环形放大器的特性来代替每个流水线级中的子ADC。原型ADC测得SNDR、SNR和SFDR分别为56.6 dB（9.11 B）、57.5 dB和64.7 dB，输入奈奎斯特频率采样速率为100 MS/s，功耗为2.46 mW。
The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. This paper presents a self-biased ring amplifier scheme that makes the ring amplifier more practical and power efficient while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. We introduce an improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto-zero switch. Furthermore, a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage. The prototype ADC has measured SNDR, SNR and SFDR of 56.6 dB (9.11 b), 57.5 dB and 64.7 dB, respectively, for a Nyquist frequency input sampled at 100 MS/s, and consumes 2.46 mW.