Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
复制标题
通过辅因子减少插值进行多错误逻辑校正的多补丁生成
DOI：
--
复制
发表时间：
2012
期刊：
影响因子：
--
通讯作者：
Chung
中科院分区：
文献类型：
--
作者：
Kai;Po;Chun;Chung
对于具有多个功能错误的设计，通常需要多个补丁来校正设计。以前的工作逻辑整流仅限于单固定或部分固定整流。换句话说，在一次迭代中只能修复一个或部分错误行为。因此，这可能会导致不必要的大补丁，甚至无法纠正。在本文中，我们提出了一个多补丁生成技术的插值与余因子减少。特别是，我们的方法同时考虑设计中的多个错误，并生成多个补丁来修复这些错误。实验结果表明，所提出的方法是有效的一组大型电路，包括从工业寄存器传输级（RTL）设计综合的电路。
For a design with multiple functional errors, multiple patches are usually needed to correct the design. Previous works on logic rectification are limited to either single-fix or partial-fix rectifications. In other words, only one or part of the erroneous behaviors can be fixed in one iteration. As a result, it may lead to unnecessarily large patches or even failure in rectification. In this paper, we propose a multi-patch generation technique by interpolation with cofactor reduction. In particular, our method considers multiple errors in the design simultaneously and generates multiple patches to fix these errors. Experimental results show that the proposed method is effective on a set of large circuits, including the circuits synthesized from industrial register-transfer level (RTL) designs.