Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice
Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice
复制标题
硅晶格扭曲导致 3D-LSI 器件特性恶化
DOI：
10.1109/ted.2013.2295463
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发表时间：
2014
影响因子：
3.1
通讯作者：
and Mitsumasa Koyanagi
中科院分区：
文献类型：
--
作者：
Mariappan Murugesan,Yasuhiko Imai,Shigeru Kimura;Takafumi Fukushima;Ji Cheol Bea,Hisashi Kino;Kang-Wook Lee;Tetsu Tanaka;and Mitsumasa Koyanagi
利用同步辐射辅助微区X射线衍射技术研究了50 μ m厚Cu-Sn μ凸点上大规模集成电路（LSI）芯片的硅晶格畸变。上芯片的顶表面和底表面分别经历0.25%和0.1%的拉伸应变（相当于450和200 MPa的拉伸应力）。Si [004]面在μ凸点和凸点-空间区域的最大倾斜度分别为+0.45 °和-0.25°。拉曼光谱显示，上层堆叠芯片在μ凸块和凸块空间区域上分别经历约1000 MPa的张应力和约-200 MPa的压应力。3D-LSI中的Si晶格畸变分别导致n型和p-MOSFET器件的导通电流特性发生4%和12%的变化。
Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45°and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.