Bounding Cache-Related Preemption Delay for Real-Time Systems
Bounding Cache-Related Preemption Delay for Real-Time Systems
复制标题
实时系统的边界缓存相关抢占延迟
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
Chong
中科院分区：
文献类型：
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作者：
Chang;Kwangpo Lee;Joosun Hahn;Yangmin Seo;S. Min;Rhan Ha;Seongsoo Hong;C. Park;Minsuk Lee;Chong
如今，几乎所有的计算机系统都使用高速缓冲存储器来弥补处理器和主存储器之间不断增大的速度差距。然而，它在多任务计算机系统中的使用引入了额外的抢占延迟，这是由于重新加载在抢占期间被替换的存储块。这种与缓存相关的抢占延迟在实时计算系统中造成了严重的问题，在实时计算系统中，可预测性是最重要的。提出了一种针对指令缓存的固定优先级抢占调度中与缓存相关的抢占延迟的分析和限界方法。所提出的技术在两个重要方面改进了以前的技术。首先，在计算与高速缓存相关的抢占延迟时，该技术考虑了被抢占的任务和在抢占期间执行的任务集之间的关系。其次，该技术考虑了任务的阶段性，以消除许多不可行的任务交互。这两个特征被表示为线性规划问题的约束，该线性规划问题的解给出了与高速缓存相关的抢占延迟的保证上界。本文还将提出的技术与以前使用随机生成任务集的技术进行了比较。结果表明，当任务集利用率为0.6时，根据缓存填充时间的不同，该方法对最坏情况响应时间预测的改善幅度在5%到18%之间。结果还表明，随着缓存填充时间的增加，性能的改善也在增加，这表明，如果当前处理器和主存之间的速度差距继续扩大，那么通过该技术准确预测与缓存相关的抢占延迟变得越来越重要。
Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap between the processor and main memory. However, its use in multitasking computer systems introduces additional preemption delay due to the reloading of memory blocks that are replaced during preemption. This cache-related preemption delay poses a serious problem in realtime computing systems where predictability is of utmost importance. We propose an enhanced technique for analyzing and thus bounding the cache-related preemption delay in fixed-priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache-related preemption delay. Second, the technique considers the phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache-related preemption delay. This paper also compares the proposed technique with previous techniques using randomly generated task sets. The results show that the improvement on the worst-case response time prediction by the proposed technique over previous techniques ranges between 5 percent and 18 percent depending on the cache refill time when the task set utilization is 0.6. The results also show that as the cache refill time increases, the improvement increases, which indicates that accurate prediction of cache-related preemption delay by the proposed technique becomes increasingly important if the current trend of widening speed gap between the processor and main memory continues.