Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS
Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS
复制标题
DOI：
10.1109/icsict.2018.8564936
复制
发表时间：
2018-10
期刊：
影响因子：
--
通讯作者：
Han Wang;Feilong Zhang;Cheng Li;Mengfu Di;Albert Z. H. Wang
中科院分区：
文献类型：
--
作者：
Han Wang;Feilong Zhang;Cheng Li;Mengfu Di;Albert Z. H. Wang
充电器件模型 (CDM) ESD 保护设计是 IC 面临的新兴设计挑战。芯片级CDM ESD保护电路仿真由于其建模等复杂性而极其困难。本文提出了一种用于芯片级 CDM ESD 保护电路设计验证和预测的新型 CDM 建模和电路仿真方法，该方法应用于采用代工 28nm CMOS 技术设计的 IC。
Charged device model (CDM) ESD protection design is an emerging design challenge for ICs. Chip-level CDM ESD protection circuit simulation is extremely difficult due to its complexity including modeling. This paper presents a novel CDM modeling and circuit simulation method for chip-level CDM ESD protection circuit design verification and prediction, which was applied to ICs designed in a foundry 28nm CMOS technology.