Addressing Resource Contention and Timing Predictability for Multi-Core Architectures with Shared Memory Interconnects
Addressing Resource Contention and Timing Predictability for Multi-Core Architectures with Shared Memory Interconnects
复制标题
使用共享内存互连解决多核架构的资源争用和时序可预测性
DOI：
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发表时间：
2020
期刊：
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通讯作者：
Wanli Chang
中科院分区：
文献类型：
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作者：
Haitong Wang;N. Audsley;Wanli Chang
多核架构越来越多地用于实时嵌入式系统。一般来说，此类系统具有比共享内存模块更多的处理器，可能会对内存访问造成严重干扰。这种资源争用可能会导致内存访问延迟的显着变化，从而导致整体系统性能大幅波动，这对于时间关键型应用程序来说是非常不受欢迎的。在本文中，我们解决了具有分布式内存互连的多核架构的资源争用和时序可预测性。我们关注由具有本地仲裁的流水线复用级构建的本地仲裁互连，而采用全局调度到同一架构的全局仲裁互连可能会遇到同步问题，并且需要严格协调。我们的贡献主要有三个：（i）我们分析内存访问数据路径上的资源争用，并报告准确的计算方法来限制最坏情况的行为。 (ii) 我们将本地仲裁架构和全局仲裁架构的平均情况行为与实验进行比较，证明资源共享问题导致不同的内存延迟。 (iii) 我们提出架构修改以实现资源共享的顺利进行。对具有合成内存工作负载的模拟器和 FPGA 实现的评估表明，延迟变化显着减少，有助于提高多核系统的时序可预测性。
Multi-core architectures are increasingly being used in real-time embedded systems. In general, such systems have more processors than the shared memory modules, potentially causing severe interference over memory accesses. This resource contention could lead to substantial variation on memory access latencies, and thus wide fluctuation in the overall system performance, which is highly undesirable especially for the time-critical applications. In this paper, we address resource contention and timing predictability for multi-core architectures with distributed memory interconnects. We focus on the locally arbitrated interconnect constructed by pipelined multiplexing stages with local arbitration, while the globally arbitrated interconnect employing global scheduling to the same architecture potentially suffers synchronisation issue and requires strict coordination. Our contributions are mainly threefold: (i) We analyse the resource contention across the memory access data path, and report the accurate calculational method to bound the worst-case behaviour. (ii) We compare the average-case behaviour of the locally arbitrated and the globally arbitrated architectures with experiments, demonstrating varying memory latencies caused by the resource sharing issue. (iii) We propose an architectural modification to smooth resource sharing. Evaluations on simulators and FPGA implementations with synthetic memory workload show that the latency variation is significantly reduced, contributing towards timing predictability of multi-core systems.