Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions

Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions
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特别会议:硬件安全 CAD - 自动化是采用解决方案的关键

DOI:
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发表时间:
2021
期刊:
IEEE VLSI Test Symposium
影响因子:
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通讯作者:
Alric Althoff
Alric Althoff
中科院分区:
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文献类型:
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作者:
Sohrab Aftabjahani;R. Kastner;M. Tehranipoor;Farimah Farahmandi;J. Oberg;Anders Nordstrom;Nicole Fern;Alric Althoff

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尽管硬件安全在过去十多年来受到了极大的关注,但工业、学术界和政府的安全设计和验证工程师和研究人员仍然没有配备成熟的安全感知工具集来自动有效地分析不同类型的安全漏洞的设计,以检测和修复安全问题,或在设计中高效、轻松地构建安全性。尽管有这样的需求,但目前还没有一个具有安全意识的电子设计自动化(EDA)或计算机辅助设计(CAD)工具的生态系统,而安全和验证工具的商业设计仍处于起步阶段。然而,已有许多研究工作试图提出安全分析引擎并提供解决方案,以解决不同类别的安全问题,如数据泄漏、访问控制违规、侧通道泄漏、硬件木马和恶意更改,以及物理攻击、故障注入攻击、逆向工程攻击和芯片伪造或生产过剩攻击的漏洞。本文介绍了几位学术和行业研究人员所建立的基础,他们一直在支持安全感知CAD工具生态系统的实现,重点是SoC设计的硬件安全覆盖和故障注入评估,以及电子设计集成的安全保证标准化。
Although hardware security has received significant attention in the past decade or so, security design and validation engineers and researchers in industry, academia, and government have not still been equipped with a mature security-aware toolset to automatically and effectively analyze designs for various types of security vulnerabilities at different to detect and fix the security issues or build security in designs efficiently and easily. Despite such a demand, currently, there is not an ecosystem of security-aware Electronic Design Automation (EDA) or Computer-Aided Design (CAD) tools whereas the commercial design for security and validation tools are still in their infancy. However, there exist many research works that try to come up with security analysis engines and provide solutions to address different classes of security issues such as data leakage, access control violation, side-channel leakage, hardware Trojans and malicious changes, and vulnerabilities to physical attacks, fault-injection attacks, reverse engineering attacks, and chip counterfeiting or overproduction attacks. This paper presents the foundation established by several academic and industry researchers who have been supporting the realization of an ecosystem of security-aware CAD tools with their focus on hardware security coverage and fault-injection assessment for SoC designs, and security assurance standardization for electronic design integration.