Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM
Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM
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DOI：
10.1145/2897937.2898106
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发表时间：
2016-06
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通讯作者：
Huizhang Luo;J. Hu;Liang Shi;C. Xue;Qingfeng Zhuge
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作者：
Huizhang Luo;J. Hu;Liang Shi;C. Xue;Qingfeng Zhuge
自旋转移扭矩随机存取存储器(STT-RAM)由于具有较好的可扩展性和较低的泄漏功耗，被认为是取代SRAM成为下一代高速缓冲存储器的候选存储器。最近，为了进一步提高数据密度，提出了2位多层单元(MLC)STT-RAM。然而，MLC STT-RAM的一个关键缺点是其硬磁区和软磁区的磁化方向不能同时反转到两个相反的方向，这导致了状态转变的两步问题。两步状态转换将显著影响MLC STT-RAM的寿命，因为在软域中浪费了翻转。为了解决这一问题，提出了一种新的两步状态转移最小化(TSTM)方案，以提高MLC STT-RAM在缓存设计中的使用寿命。其基本思想是通过牺牲某些单元作为辅助标志，可以很好地消除STT-RAM中的两步状态转换。实验结果表明，该方案可以将MLC STT-RAM的寿命提高到318.5%。
Spin-transfer torque random access memory (STT-RAM) is considered as a promising candidate to replace SRAM as the next generation cache memory since it has better scalability and lower leakage power. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to further increase data density. However, a key drawback for MLC STT-RAM is that the magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step problem in state transitions. Two-step state transitions would significantly impact the lifetime of MLC STT-RAM due to the wasted flips in the soft domains. To solve the problem, this paper proposes a novel two-step state transition minimization (TSTM) scheme, to improve the lifetime of MLC STT-RAM when it is employed in cache design. The basic idea is by sacrificing certain cells as auxiliary flags, the two-step state transitions in STT-RAM can be well eliminated. Experimental results show that the proposed scheme can improve the lifetime of MLC STT-RAM to 318.5%.