Realization of Conductive n‐Type Doped α‐Ga2O3 on m‐Plane Sapphire Grown by a Two‐Step Pulsed Laser Deposition Process

Realization of Conductive n‐Type Doped α‐Ga2O3 on m‐Plane Sapphire Grown by a Two‐Step Pulsed Laser Deposition Process
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通过两步脉冲激光沉积工艺在 m 面蓝宝石上实现导电 n 型掺杂 α-Ga2O3

DOI:
10.1002/pssa.202200721
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发表时间:
2022
期刊:
physica status solidi (a)
影响因子:
--
通讯作者:
M. Grundmann
M. Grundmann
中科院分区:
--
文献类型:
--
作者:
S. Vogt;Clemens Petersen;M. Kneiß;D. Splith;T. Schultz;H. von Wenckstern;Norbert Koch;M. Grundmann

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研究了脉冲激光两步法在m面蓝宝石衬底上生长的未掺杂和掺杂α-Ga_2O_3薄膜的结构和电学性质。在电活性薄膜下方引入了未掺杂的α-Ga_2O_3缓冲层,以提高晶体质量,并使α相在较低的衬底温度下稳定下来,从而实现充分的掺杂。施主掺杂TiN、Ge和Si分别在低于600 °C的临界衬底温度下实现。对掺锡样品的深度分辨X射线光电子能谱测量表明,与表面相比,块体薄膜中的锡含量较低,并且在较高的衬底温度下,锡的掺入量较低,这表明解吸或浮选过程决定了掺杂的掺杂量。对于锡和锗掺杂,电子迁移率分别达到17cm2 V−1 S−1(1 4×10 19 cm−3)和37 cm2 V−1 S−1(3 7×10 18 cm−3)。在此基础上,确定了获得Ti/Al/Au欧姆层叠层的适宜温度范围为680~700 K的窄窗口。在较高的退火温度下,观察到薄膜的电学性能恶化,这表明有必要为α-Ga2O3基器件开发低温接触工艺。
Structural and electrical properties of undoped and doped α‐Ga2O3 thin films grown by pulsed laser deposition on m‐plane sapphire in a two‐step process are presented. A buffer layer of undoped α‐Ga2O3 is introduced below the electrically active thin film to improve the crystal quality and enable the stabilization of the α‐phase at lower substrate temperatures for sufficient dopant incorporation. Donor doping of the active layers with tin, germanium, and silicon, respectively, is realized below a critical substrate temperature of 600 °C. Depth‐resolved X‐ray photoelectron spectroscopy measurements on tin‐doped samples reveal a lower amount of tin in the bulk thin film compared to the surface and a lower tin incorporation for higher substrate temperatures, indicating desorption or float‐up processes that determine the dopant incorporation. Electron mobilities as high as 17 cm2 V−1 s−1 (at 1.4 × 10 19 cm − 3 ) and 37 cm2 V−1 s−1 (at 3.7 × 10 18 cm − 3 ) are achieved for tin‐ and germanium doping, respectively. Further, a narrow window of suitable annealing temperature from 680 to 700 K for obtaining ohmic Ti/Al/Au layer stacks is identified. For higher annealing temperatures, a deterioration of the electrical properties of the thin films is observed suggesting the need for developing low temperature contacting procedures for α‐Ga2O3‐based devices.