Simulations of sub-100nm strained Si MOSFETs with high-k gate stacks
Simulations of sub-100nm strained Si MOSFETs with high-k gate stacks
复制标题
具有高 k 栅极堆叠的 100 nm 以下应变 Si MOSFET 的仿真
DOI：
--
复制
发表时间：
2004
期刊：
影响因子：
--
通讯作者：
Barker
中科院分区：
文献类型：
--
作者：
Yang;Watling;Adam;Asenov;Barker
硅MOSFET的规模超过90纳米技术节点需要性能助推器，以维持高性能固有速度的年度增长（2003）。一种可能的解决方案是使用应变Si沟道的传输增强FET。降低等效氧化物厚度（EOT）的栅极漏电流所需的高k值MOSFET预计将取代65 nm节点周围的SiO/sub 2/，以实现进一步的缩放。然而，在Si之上实现高质量的高k掺杂是有问题的（Wilk等人，2001年）。除了这些技术问题之外，具有高k值的MOSFET的基本缺点是由于强的软光学（SO）声子散射导致的迁移率退化（Fischetti等人，2001年）。在这项工作中，我们研究了界面粗糙度和软光学声子散射对传统和应变Si n-MOSFET的性能与高k值使用自洽系综Monte Carlo（EMC）器件模拟器的影响。示出了模拟的器件结构。
Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to sustain the annual increase of intrinsic speed of high-performance (2003). One potential solution is transport enhanced FETs using strained Si channels. High-k dielectrics required to reduce the gate leakage current for equivalent oxide thickness (EOT) are expected to replace SiO/sub 2/ around the 65 nm node in order to enable further scaling. However, achieving high-quality high-k dielectrics on top of Si is problematic (Wilk et al., 2001). Aside from these technological issues, a fundamental drawback of MOSFETs with high-k dielectrics is the mobility degradation due to strong soft optical (SO) phonon scattering (Fischetti et al., 2001). In this work we study the impact of interface roughness and soft optical phonon scattering on the performance of conventional and strained Si n-MOSFETs with high-k dielectrics using a self-consistent ensemble Monte Carlo (EMC) device simulator. The simulated device structures are illustrated.